1. Field of the Invention
The present application relates to mastering and arbitration. More specifically, the present application relates to methods and apparatus for allowing multiple master components in a system to access multiple slave components simultaneously.
2. Description of Related Art
Conventional systems using a shared bus architecture have several drawbacks. In typical systems with a bus architecture, a single arbitrator controls communication between multiple master components and multiple slave components. To access a slave component, a master component requests control of the bus from the single system bus arbitrator. If no other master component is using the bus at a given moment, the system bus arbitrator can grant the request and provide control of the bus to the master component. The master can then send information to the target slave. However, if another master component is using the bus, the master component would have to wait for access from the system bus arbitrator as only one master component can use the bus at any given time. That is, a first master component wishing to access a first slave component would have to wait until a second master component finished accessing a second slave component because of the requirement that only one master can use the bus at a time. The rule applies even if the first master and the first slave components are idle.
It is therefore desirable to provide improved methods and apparatus for master components to access slave components in a system.